Combinational circuits timing analysis deals primarily with propagation delay issues. Sequential circuits have additional specific timing characteristics that must be satisfied in order to prevent metastability, including setup time, hold time, and minimum clock period. Hence it is important to identify the type of circuit because our timing calculation approach differs accordingly. Designers of sequential devices must specify these important timing characteristics in order to allow the device to be used without error.
Combinational Circuits
Propagation Delay (tpd)
Propagation Delay indicates the amount of time needed for a change in the logic input to result in a permanent change at an output.
Combinational propagation delays are additive. It is possible to determine the propagation delay of a larger combinational circuit by adding the propagation delays of the circuit components along the longest path.
Contamination Delay (tcd)
Contamination Delay indicates the amount of time needed for a change in the logic input to result in an initial change at an output.
The determination of the contamination delay of the combined circuit requires identifying the shortest path of contamination delays from input to output.
timingfig1.
Example
Timingex1
Longest delay is through path w-x-z.
Hence propagation delay tpd = 3+2 = 5 ns.
Shortest delay is through path y-z.
Hence contamination delay tcd = 1+1 = 2 ns.
Sequential Circuits
Propagation Delay (tclk-Q-max)
Propagation Delay in sequential circuits indicates the amount of time needed for a change in the flip-flop clock input (e.g. rising edge) to result in a permanent change at the flip-flop output (Q).
Contamination Delay (tclk-Q-min)
Contamination Delay in sequential circuits indicates the amount of time needed for a change in the flip-flop clock input (e.g. rising edge) to result in the initial change at the flip-flop output (Q).
Metastability
Set up time (tS)
Setup time is a timing parameter associated with Sequential Devices. The Setup time is used to meet the minimum pulse width requirement for the first (Master) latch makes up a flip flop is. More simply, the setup time is the amount of time that an input signal (to the device) must be stable (unchanging) before the clock ticks in order to guarantee minimum pulse width and thus avoid possible metastability.
Setup violations occurs when the data path is too slowcompared to the clock speed.
The designer can fix the setup violations by reducing the delay in the data path. Designer can reduce the clock speed to fix the setup violation, but it is going to be a poor design technique.
Hold time (tH)
Hold time is also a timing parameter associated with Flip Flops and all other sequential devices. The Hold time is used to further satisfy the minimum pulse width requirement for the first (Master) latch that makes up a flip flop. The input must not change until enough time has passed after the clock tick to guarantee the master latch is fully disabled. More simply, hold time is the amount of time that an input signal (to a sequential device) must be stable (unchanging) after the clock tick in order to guarantee minimum pulse width and thus avoid possible metastability.
Hold violations occurs when data is too fast compared to the clock speed.
Constraint to prevent hold time violation is
thold + tskew≤tclock-Q-min + tlogic-min
If hold violations are not fixed before the chip is made, lot of problem occurs unlike setup violation where the clock speed can be reduced. To fix hold violations, designer can add more delay to the data path.
